The present invention relates to an electric erasable semiconductor non-volatile memory device and a method of manufacturing the same.
In FIGS. 2A and 2B, there is shown the general structure of an electric erasable semiconductor non-volatile memory cell (hereinafter referred to as the "EEPROM cell") wherein FIG. 2A is a plan view of the memory cell and FIG. 2B is a sectional view taken along C--C line of FIG. 2A. As shown, a N-type source region 2 and a N-type drain region 3 are provided over the surface of a P-type silicon substrate 1 through a channel forming region 4A.
On the N-type drain region 3 there is formed a silicon oxide film 5 thereby forming a tunnel region 5A. Further, on the channel forming region 4A there is formed a floating gate electrode 6 through a gate insulating film 24 so as to partly overlap the source region 2 and the drain region 3. The floating gate electrode is strongly capacity-coupled to a control gate electrode 8 provided through a control insulating film 7.
The conductance of the channel forming region 4A between the source region 2 and the drain region 3 changes depending on the potential of the floating gate electrode 6. Therefore, by changing the amount of electrical charge in the floating gate electrode, it is possible to store information as a non-volatile one. In order to change the amount of charge in the floating gate electrode, a tunnel insulating film 5 is partially formed between the drain region and the floating gate electrode thereby forming a tunnel region. When the portion of the drain region serving as the tunnel region is applied with a high voltage of about 15V with respect to the control gate electrode, the electrons in the floating gate electrode flow into the drain region through the tunnel insulating film so that the amount of electrical charge in the floating gate electrode changes.
A memory array is provided by arranging The EEPROM cells shown in FIGS. 2A in both X- and Y- directions in the form of a matrix. Each of the EEPROM cells allows non-volatile information to be programmed by generating a high voltage of about 15V through a boosting circuit provided in an IC. Accordingly, the EEPROM IC can perform reading and programming operations by a single power source of 5V, for example.
However, the EEPROM cell to be used for the conventional single power source EEPROM IC has had a tunnel region 5A inside its drain region as shown in FIG. 2A in order to reduce the magnitude of current flowing through the drain region at the time of programming. That is, the tunnel region has been spaced apart from a field insulating film 9A.
Therefore, it has been difficult to manufacture a compact and high-density single power source EEPROM IC. since the memory cell for forming one bit has required a large area.
Accordingly, an object of the present invention is to provide a compact and high-density EEPROM IC at low cost in such a manner that each one bit memory cell is reduced by narrowing the channel forming width.